MIGUEL A. FORJAN
1241 S. Westgate Avenue, #103
Los Angeles, CA 90025
Resourceful and experienced product engineer with strong technical background in new product development, characterization, high-speed bench test, release/transfer product to Production/Manufacturing and product debug.
11 years product engineering experience (yield analysis, reducing costs, transfer product to Production)
Strong data analysis skills (SPC, Cpk) and fab process (CMOS, GaAs, SiGe)
Support product qualification (HTOL, THB, ESD HBM/CDM)
Strong technical leader, highly motivated and eager to accept new challenges
Sierra Monolithics Inc., Redondo Beach, CA Dec 2006 to Jan 2009
Worked closely with Design Engineering, Marketing and Manufacturing to manage Wafer Sort, characterization, qualification, yield and production ramp-up for the 40-45Gbps SerDes products (Gamma 2, Gamma 3). Analyzed parametric WAT data and worked closely with IBM (wafer supplier) to meet process control requirements. Correlated PCM data to Wafer Sort and Final Test data to improve and optimize yield, performance and manufacturability. Interfaced with applications and marketing for customer characterization and failure analysis requirements. Supported product characterization of 40-45Gb/s Mux/Demux chip sets using lab equipment and test bench. Worked with test engineering to debug bench test issues. Managed product reliability/qualification tasks and analyzed reliability data. Supported RMA’s. Provided technical support as the responsible product engineer to Manufacturing/Operations.
Vitesse Semiconductor Corporation, Camarillo, CA Jan 1998 to Nov 2006
Senior Member of Technical Staff (Product Engineering) Jan 2002 to Nov 2006
Provided technical leadership to a group of product/test engineers involved in high-speed testing, debug and volume production support of 12.5Gb/s and 10Gb/s Mux/Demux chips, 10Gb/s Transceivers and Clock/data Recovery chips. Provided key engineering support to major products, identified product problems and provided timely feedback to design. Correlated yield to fab parameters and provided feedback to fab, which resulted in higher and more repeatable product yields. Developed stable and repeatable high-speed bench tests to support volume production/manufacturing. Interfaced with design, fab process, applications, marketing and manufacturing to ensure smooth product transition from fab to customer.
Member of Technical Staff (Product Engineering) Jan 1998 to Dec 2001
Led the high-speed 12.5GHz test development effort to support volume production of 10Gb/s FEC Mux/Demux chips and stand-alone CDR chips. This included high-speed DUT board (PCB) design, designing test methods and writing test software in C using GPIB interface. Identified the root cause of yield problems of high volume products and worked with design and fab process to fix the problems. Resolved customer problems by developing additional screens and working with design to fix root cause of failure. Responsible for accurately forecasting product yields. Responsible for supporting the evaluation and debug of new products using wafer probers, VLSI testers, test bench lab equipment (BERT) and high-speed fixture scopes. Responsible for yield analysis, improvement, problem product resolution and new product/technology introduction. Supported yield analysis and product debug on a variety of ASICs. Improved yields by eliminating test issues, identifying key fab parametrics, which correlated well to major pareto failure modes. Developed bench test setups to debug and characterize ASIC devices that failed at customers’ site. Resolved product-related production problems. Optimized test flows for yield and cost reduction. Identified, analyzed and recommended solutions to component yield issues. Led and evaluated prototype builds up to characterization and testing.
Master of Science in Electrical Engineering, Southern Illinois University, Edwardsville, IL December 1997
Master of Science in Physics, Georgia Institute of Technology, Atlanta, GA June 1993
Bachelor of Science in Physics, Southern Illinois University, Edwardsville, IL August 1991
C, GPIB, FORTRAN, awk, Shell scripts, UNIX, Windows O/S, HSPICE, MATLAB, Mentor Graphics, Cornerstone, Sun SPARCs
Focus Ion Beam—IDS P2X User Training and SX100 ASAP programming (Schlumberger Technologies),
SONET Overview (Bellcore), Time Management (Franklin &Colby), Multiple Projects Management (Fred Pryor), ISO 9000/9001 Quality System Course
PERSONAL U.S. Citizen
REFERENCES Available upon request